Principal Design Engineer
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Overview
Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world‑class sales, marketing, and support teams, developing programmable logic solutions that change the industry. Our focus is on R&D, product innovation, and customer service, with total commitment to quality and competitiveness.
Responsibilities & Skills
Lattice Semiconductor is seeking a Principal to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunities to contribute, learn, innovate, and grow.
- Full‑time Principal Engineer position located in Pune, India.
- Lead the design and development of complex components of FPGA, ensuring performance, power, and area targets.
- Expert in subsystem development, ensuring high‑quality, reliable design; conduct regular reviews and audits.
- Work closely with the architecture team to define micro‑architecture and design specifications.
- Serve as technical expert in SoC design, providing guidance and support to other engineers.
- Educator and student : teach best‑known methods to the FPGA team and learn from the team.
Accountabilities
Key contributor to FPGA design efforts.Drive logic design of key FPGA system & full chip, accelerating design time and improving quality.Maintain design quality with regular reviews and audits.Collaborate with cross‑functional teams : program management, package design, pre / post‑silicon validation.Develop strong relationships with worldwide teams.Drive continuous improvement, staying up‑to‑date with industry trends.Occasional travel as needed.Required Skills
BS / MS / PhD in Electronics Engineering, Electrical Engineering, Computer Science or equivalent.16+ years of experience in driving logic design across multiple silicon projects.Expertise in SoC integration, micro‑architecture definition, and third‑party IP selection.Experience with ARM processor, AXI, AMBA bus, ENET, PCIE, USB, safety / security protocols, debug architecture.Leading projects throughout the design cycle with cross‑organization collaboration.Familiarity with FPGA designs, use‑cases, and design considerations (plus).Proof of working across multiple groups / sites and time zones.Benefits
Lattice offers a comprehensive compensation and benefits program to attract, retain, motivate, reward, and celebrate employees.
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